PhD Position F/ M Trustworthy AI hardware architectures

PhD Position F/M Trustworthy AI hardware architectures

Level of qualifications required: Graduate degree or equivalent

Function: PhD Position

About the research centre or Inria department

The Inria Rennes - Bretagne Atlantique Centre is one of Inria's eight centres and has more than thirty research teams. The Inria Center is a major and recognized player in the field of digital sciences.

Context

Context and background: Nowadays, there is a growing need to distribute Artificial Intelligence (AI) applications from the cloud to edge devices, where computation is largely performed on distributed Internet of Things (IoT) devices. This trend addresses issues related to data privacy, bandwidth limitations, power consumption reduction, and low latency requirements.

The direct consequence is the intense activity in designing custom and embedded Artificial Intelligence Hardware architectures (AI-HW) to support energy-intensive data movement, speed of computation, and large memory resources that AI requires. Moreover, explaining AI decisions, referred to as eXplainable AI (XAI), is highly desirable to increase trust and transparency in AI.

AI-HW, similar to traditional computing hardware, is subject to faults that can have several sources: variability in fabrication process parameters, latent defects, or environmental stress. One of the overlooked aspects is the role that HW faults can have in AI decisions. Recent studies have shown that AI-HW is not always immune to HW errors, which can jeopardize explainability efforts.

Therefore, before explaining the decision of an AI algorithm, the reliability of the hardware executing the AI algorithm needs to be guaranteed, even in the presence of hardware faults.

Assignment

The goal of the Ph.D. thesis is to study the impact of hardware faults on AI decisions and algorithms developed to explain AI models. The objective is to make AI-HW reliable by understanding how hardware faults can impact AI and XAI decisions and how to mitigate those impacts efficiently.

Main activities

The Ph.D. student will:

• Analyze the possible failure mechanisms affecting the hardware;
• Derive the corresponding hardware faults from the knowledge of failure mechanisms;
• Analyze their impact on AI and XAI results, in terms of accuracy degradation;
• Design low-cost fault tolerance approaches to efficiently detect/correct HW faults.

Skills

Required technical skills:

• Good knowledge of computer architectures and embedded systems
• Machine Learning (pytorch/tensorflow)
• HW design: VHDL/Verilog basics
• Basic programming knowledge (C/C++, python)
• Experience with High Level Synthesis (HLS) is a plus
• Experience in fault tolerant architectures is a plus

Candidates must have a Master’s degree (or equivalent) in Computer Science, Computer Engineering, or Electrical Engineering.

Languages: proficiency in written and spoken English required.

Relational skills: The candidate will work in a research team and must present progress clearly.

Other valued appreciated: Open-mindedness, strong integration skills, and team spirit.

Most importantly, we seek highly motivated candidates.

Benefits package

• Partial reimbursement of public transport costs
• Possibility of teleworking (90 days per year)
• Partial payment of insurance costs

Remuneration

Monthly gross salary: 2100 euros for the first two years and 2200 euros for the third year.

Instructions to apply

Please submit online: your resume, cover letter, and letters of recommendation.

Defence Security: This position may be situated in a restricted area. Authorization to enter is granted by the director of the unit.

Recruitment Policy: All Inria positions are accessible to people with disabilities.