Snabbfakta
-
- Palaiseau
Ansök senast: 2024-07-21
Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC Designs H/ F
Position description
Category
Electronics components and equipments
Contract
Fixed-term contract
Job title
Research Engineer in AI-assisted Methods for Model Generation and Simulation of SoC Designs H/F
Socio-professional category
Executive
Contract duration (months)
24
Job description
We are looking for a highly skilled and motivated Research Engineer to join our team to develop cutting-edge technology in the field of Electronic Design Automation (EDA).
In the context of a national project, you will be responsible for developing a simulation environment for chiplet-based SoC architecture, using AI-driven methodologies to improve existing EDA flow. You will work in close cooperation with our interdisciplinary team of engineers and researchers on innovative research projects at European and national level as well as in industrial partnerships.
Responsibilities:
- Develop and implement an AI-based model generation methodologies for computing platform simulation. The generated models will cover functional behavior for software validation as well as performance prediction of the hardware platform.
- Integration of the generated models into a simulation environment (virtual prototype) targeting chiplet-based architectures
- Evaluate the performance and effectiveness of the proposed solution.
- Stay ahead of advances and best practices in AI, SoC design, and related fields and contribute to CEA's intellectual property through patents and publications.
Applicant Profile
Required qualifications:
- Ph.D. or Master's degree in Electrical Engineering, Computer Science, or a related field.
- Proficiency in programming languages such as C/C++ and Python, and experience with relevant libraries/frameworks.
- Strong background in AI, machine learning, and deep learning methods, such as GNN and LLM.
- Experience in SoC high-level simulation frameworks utilizing QEMU and SystemC or lower-level RTL description languages (e.g. VHDL, Verilog, SystemVerilog).
- A strong willingness to learn.
Preferred Qualifications
- Solid understanding of SoC architectures and EDA tools.
- Excellent problem-solving skills and ability to work both independently and collaboratively in a fast-paced research environment.
- Strong communication and interpersonal skills with the ability to present complex ideas clearly and effectively.
Position location
Site
Saclay
Job location
France, Ile-de-France, Essonne (91)
Location
Palaiseau
Candidate criteria
Languages
Requester
Position start date
03/06/2024
